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1 of 40 rev: 021607 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds2792 provides a user-programmable fuel gauge solution for li-ion and nimh chemistry battery packs. a low-power, 16-bit maxq20 microcontroller with generous program and data memory, combined with an accurate measurement system for battery current, voltage, and temperature provide the ideal platform for customized fuel-gauge algorithms. eeprom data memory supports nonvolatile (nv) in-pack storage of charge parameters, cell characteristics, usage history, and manufacturing/lot tracking data. applications digital video cameras slr digital still cameras subnotebook pcs and ultra-portable pcs industrial pdas, handheld computers, and gps functional diagram maxq is a registered trademark of maxim integrated products, inc. features ? accurate current measurement for coulomb counting (current accumulation) 1.5% 4v over 64mv input range 1.5% 267a over 4.2a range using an external 15m series resistor ? high-resolution current reporting 12-bit + sign average every 0.88ms 15-bit + sign average every 2.8s ? three voltage measurement sources 10-bit average from vin1, vin2?vin1, and vx inputs ? temperature measurement 10-bit using on-chip sensor ratiometric input for external thermistor (vx) ? 16-bit maxq20 low-power microcontroller efficient c-language programming 8k words total program memory: 4k words eeprom program memory 4k words rom program memory 64 words data eeprom 256 words data ram password-protected programming ? on-chip, low drop-out regulator 2.5v to 10v operating range ? sha-1 hash algorithm in rom ? 19.2kbps uart interface ? internal oscillator: no crystal required ? low-power consumption 1.5ma cpu mode (1mhz), 145a analog mode, 50a sleep mode ordering information part temp range pin-package ds2792g+ -20oc to +70oc tdfn-28 + denotes lead-free package. contact factory concerning mask rom devices. pin configuration appears at end of data sheet. ds2792 programmable fuel gauge with uart interface www.maxim-ic.com
ds2792 programmable fuel gauge with uart interface 2 of 40 absolute maximum ratings v dd , vin2 to v ss ............................................................................................................................... ........ -0.3v to +12v p0.4, p0.5 to v ss ............................................................................................................................... . -0.3v to v b +0.3v av ss to v ss ............................................................................................................................... ............... -0.3v to +0.3v all other pins to v ss ............................................................................................................................... ... -0.3v to +6v txd, p0.0?p0.5 continous sink current ............................................................................... 20ma each, 50ma total operating tem perature range.................................................................................................... ..........-40oc to +85oc storage temperat ure range ...................................................................................................... .........-55oc to +125oc soldering temperat ure ................................................................................see ipc/je dec j-std-020 sp ecification stresses beyond those listed under ?absolute maximum ratings? may c ause permanent damage to the device. these are stress rating s only, and functional operation of the device at t hese or any other conditions beyone those indicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rati ng conditions for extended peri ods may affect device. recommended dc operat ing characteristics (v dd = 2.5v to 10v, t a = -20c to +70c, unless otherwise noted. typical values are at t a = +25c, v dd = 5.0v.) parameter symbol conditions min typ max units supply voltage v dd (note 1) +2.5 +10 v voltage range: vin1, txd, rxd, p0.0?p0.3, sns1, sns2 (note 1) -0.3 5.5 v voltage range: p0.4?p0.5 (note 1) -0.3 v b + 0.3 v voltage range: vin2 (note 1) -0.3 +10 v voltage range: vx (note 1) -0.3 v b + 0.3 v output voltage: v b v vb v dd > 3.5v, i o = 2ma, (note 1) 3.0 3.3 3.6 v electrical characteristics (v dd = 2.5v to 10v, t a = -20c to +70c, unless otherwise noted. typical values are at t a = +25c, v dd = 5.0v.) parameter symbol conditions min typ max units i sleep sleep mode (note 2) 25 50 a i susp suspend mode (note 3) 25 50 a i analog analog mode (note 4) 110 145 a supply current i cpu cpu mode (note 5) 0.8 1.5 ma power-on reset threshold v reset 1.0 1.6 2.2 v brownout threshold v bo (note 10) 2.0 2.2 2.4 v regulator drop-out v do:vb v dd = 2.5v, i vb = 2.0ma, (note 6) 0.15 v current measurement input range i fs v is1 ?v is2 -64 +64 mv current measurement resolution i lsb 15.625 v/r sns 0 o c t a +50 o c -0.5 +0.5 current measurement gain error i gerr -1 +1 % full scale current measurement offset error i oerr -7.8 +7.8 v/r sns accumulated current range q fs -204.8 +204.8 mvh/r sns accumulated current resolution q lsb 6.25 vh/r sns oben = 1 -94 0 vh/day accumulated current offset q ca oben = 1, r sns = 0.015 ? -6.3 0 mah/day temperature measurement range t fs -40 +85 o c temperature measurement lsb t lsb 0.125 o c temperature measrement error t err -3 +3 o c
ds2792 programmable fuel gauge with uart interface 3 of 40 parameter symbol conditions min typ max units vin1 input range (vin1?v ss ) v fs1 (notes 1, 7) 0 4.99 v vin1 lsb v lsb1 4.88 mv vin2 input range (vin2?vin1) v fs2 (notes 1, 7) 0 4.99 v vin2 lsb v lsb2 4.88 mv vin1, vin2 gain error v gerr -1 +1 % vin1, vin2 offset v oerr -1 +1 lsb vx input range (vx?v ss ) v fsx (note 1) 0 v b v vx lsb v lsbx v b /1024 ? vx error v errx -1 +1 % full scale vin1, vin2, vx input resistance r in 15 m ? current measurement sample frequency f sample (note 8) 1456 hz analog system clock frequency f osca 69.9 khz v dd > 2.7v, t a = +25 o c -0.7 +0.7 v dd > 2.7v, 0 o c t a +50 o c -2 +2 analog system clock error f err:osca -5 +5 % osca active 1 cpu system clock startup time t su:osci from sleep, osca inactive 700 s osca inactive 1000 khz cpu system clock frequency f osci osca active 14 x f osca khz osca inactive -20 +20 cpu system clock error f err:osci osca active f err:osca % suspend period error t err:sus -30 +30 % filter resistors is1 to sns1, is2 to sns2 r ks 7 10 13 k ? input logic high: rxd v ih:rxd (note 1) 1.5 v input logic low: rxd v il:rxd (note 1) 0.6 v input logic high: p0.0?p0.5 v ih:p0 (note 1) 0.7 x v b v input logic low: p0.0?p0.5 v il:p0 (note 1) 0.3 x v b v output logic low: txd, p0.x v ol iol = 4ma (note 1) 0.4 v p0.0?p0.3 weak pullup current i pu:p0 v pin = v ih , v dd > 2.7v bits ppu:0,1,2,3 set 0.15 22.0 a output logic high: p0.4?p0.5 v oh i pin = 1ma bits ppu:4,5 set v b - 0.4 v rxd, txd pulldown current i pd:uart v pin = v il , bits ppu:6,7 clear 0.3 1.2 3 a rxd, txd pullup current v pu:uart v pin = v il , bits ppu:6,7 set 0.3 1.2 3 a rxd, txd capacitance c uart 50 pf rxd pulse rejection t sp:uart rising and falling edges (note 9) 50 ns p0.0?p0.5 pulse rejection t sp:p0 rising and falling edges 10 ns eeprom reliability specification (v dd = 2.5v to 10v, t a = -20c to +70c, unless otherwise noted. typical values are at t a = +25c, v dd = 5.0v.) parameter symbol conditions min typ max units eeprom copy time t eec 10 15 ms eeprom copy endurance n eec t a = +50c 50,000 cycles
ds2792 programmable fuel gauge with uart interface 4 of 40 electrical characterist ics: jtag interface (v dd = 2.5v to 10v, t a = -20c to +70c, unless otherwise noted. typical values are at t a = +25c, v dd = 5.0v.) (see figure 1.) parameter symbol conditions min typ max units jtag logic reference v ref (note 1) v b 2 v tck high time t th 4.0 s tck low time t tl 4.0 s tck low to tdo output t tlq 1.0 s tms, tdi input setup to tck high t dvth 1.0 s tms, tdi input hold after tck high t thdx 4.0 s note 1: all voltages referenced to v ss . note 2: internal voltage regulator remains active in sleep mode. ra m and registers are powered to maintain contents. rxd and internal interrupts can be armed by firmware. note 3: internal voltage regulator and suspend timer are active in suspend mode. ram and registers are powered to maintain contents. note 4: internal voltage regulator and adc are active in analog mode. ram and registers are powered to maintain contents. adc data is collected and updated to registers includi ng current accumulation to acr register. note 5: maxq core fetches and executes instructions in cpu mode. note 6: parameters guaranteed by design. note 7: voltage a/d readings saturate at 4.85v. note 8: f osca = 48 f sample . note 9: the filter on rxd suppresses noise spikes at the input buffers and delays the sampling instant. note 10: v reset and v bo will never overlap. figure 1. jtag timing diagram
ds2792 programmable fuel gauge with uart interface 5 of 40 pin description pin name function 1, 7?10, 21, 25, 26, 28 n.c. no connection 2 vin2 battery voltage sense input 2 . voltage measurement on vin2 is relative to vin1. 3 vin1 battery voltage sense input 1 . voltage measurement on vin1 is relative to av ss . 4 vx auxiliary adc input . voltage measured ratiometrically with respect to v b pin voltage or absolutely with respect to internal reference. 5 txd serial interface data transmit . maximum of 19200bps. 6 rxd serial interface data recieve . maximum of 19200bps. 11 p0.0 programmable i/o pin . alternate functions: external interrupt input int0, [jtag tdi]. 12 p0.1 programmable i/o pin . alternate functions: external interrupt input int1, [jtag tms]. 13 sns2 current-sense input . sns2 attaches to the pack end of current- sense resistor. 14 is2 current filter input 2 15 is1 current filter input 1 16 sns1 current-sense input . sns1 attaches to the battery end of current- sense resistor and v ss . 17 av ss analog supply return node . av ss attaches to negative battery terminal. 18 v ss digital supply return node . v ss attaches to negative battery terminal. 19 p0.2 programmable i/o pin . alternate functions: reset input pin rst . 20 p0.3 programmable i/o pin . alternate functions: timer/counter input pin tck, [jtag tck]. 22 p0.4 programmable i/o pin . alternate function: [jtag tdo] 23 p0.5 programmable i/o pin 24 v b bias supply output . internally regulated to 3.3v. bypass v b to v ss with 0.1f. 27 v dd input supply . +2.5v to +10.0v input range. bypass v dd to v ss with 0.1 f. ? pad exposed pad. not electrically connected to ic. connect to v ss or leave floating.
ds2792 programmable fuel gauge with uart interface 6 of 40 functional diagram avg current temperature voltage2 (vin2 - vin1) aux voltage (vx - avss) maxq20 16-bit risc core jtag bootload and debug interface timer/ counter interrupt controller instruction oscillator (1mhz) precision analog oscillator 64 x 16 eeprom (data) 256 x 16 sram (data) 4k x 16 eeprom (program) 4k x 16 rom (utility) uart interface and bootloader register file dp[0] dp[1] bp[offs] p0.3/tck p0.0/tdi p0.4/tdo p0.1/tms clk div ldo regulator vb vdd_int vdd current (is1 - is2) voltage1 (vin1 - avss) a/d control vin1 vref tci p0.3 ttck0:1 analog front end adc / mux analog registers is1 is2 sns2 sns1 vss avss port pin drivers p0.0/int0/tdi p0.1/int1/tms p0.2/rst p0.3/tck p0.4/tdo p0.5 txd rxd tx int0, int1 rx sci, sdi boi, vi, ci, ti watchdog timer wdi vss_int eeprom charge pump vin2 vx suspend timer
ds2792 programmable fuel gauge with uart interface 7 of 40 typical operating circuit in figure 2, the ds2792 is connected to t he battery side of the pack protector. v dd is isolated with a 150 ? resistor. both v dd and the internally regulated voltage v b have 0.1f bypass capacitors. t he vin1 and vin2 pins sample the voltage of each cell. current flow through the cell pack is monitored by measuring the voltage drop across the sense resistor r sns . cell temperature is measured ratiometrically through the general-purpose voltage input vx. the gpio pin p0.5 gates the thermistor circuit to lim it current flow between measurements. the uart signals rxd and txd are combined into a single 3.3v bidirectiona l i/o line. the i/o circuit causes no extra current drain when idle. figure 2. example pack circ uit with regulated i/o ds2792 2-cell protection ic vdd vb vin2 vin1 vss, avss sns1 sns2 txd rxd data pack+ pack- is1 vx is2 0.1f 0.1f at103-2 1k 1k 150 10k r sns 0.1f bss84 1k 1k 1k 1k 1k 100 100 100 100 100 2n2222 2n2222 2n3906 [p0.0-p0.4] p0.5 detailed description the following is an introduction to the primary features of the ds2792 programmable 2-cell li-ion fuel gauge. more detailed descriptions of the device features can be found in the errata sheets and user's guides described later in the additional documentation section. ds2792 overview the ds2792 incorporates the 16-bit maxq20 microcontrolle r core with 16 accumulators and 16-level hardware stack. four memory bloc ks provide application co de space, utility code spac e, ram memory, and eeprom memory. specialized peripherals are integrated to perfo rm battery monitoring, coulomb counting, and uart communication functions. the maxq20 core along with the specialized peripherals provide a flexible solution for fuel gauging of li-ion or nimh battery packs. flexibility is further enhanced as the solution allows for upgrading of
ds2792 programmable fuel gauge with uart interface 8 of 40 the program and data eeprom contents over the uart in terface. updates to the program and data eeprom are protected against unauthorized writes by a 256-bit user password. a read protection bit is provided to prevent reading either eeprom. maxq20 core architecture the ds2792 employs a maxq20 low-cost, high-performance, cm os, fully static, 16-bit risc microcontroller with eeprom memory. fetch and execution op erations are completed in one cy cle without pipelining, since the instruction contains both the op code and data. the highly efficient core is supported by 16 accumulators and a 16- level hardware stack, enabling fast subroutine calling an d task switching. data can be quickly and efficiently manipulated with three internal data pointers. multiple dat a pointers allow more than one function to access data memory without having to save and restore data pointers each time. the data pointers can automatically increment or decrement following an operation, elimi nating the need for software intervention. instruction set the instruction set is composed of fix ed-length, 16-bit instructio ns that operate on registers and memory locations. the instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. special-function register s control the peripherals and are subdivide d into register modules. the family architecture is modular, so that new devices and m odules can reuse code developed for existing products. the architecture is transport-triggered. this means that writes or reads from certain register locations can also cause side effects to occur. these side effects form the basis for higher level op codes, such as addc, or, jump, etc. the op codes are implemented as move instructions between register locations, while the assembler handles the encoding, which need not be a concern to the programmer . the 16-bit instruction word is designed for efficient execution. bit 15 indicates the format for the source field of the instruction. bits 0 to 7 of the instruction represent the source for the transfer. depending on the value of the format fi eld, this can either be an immediate value or a source register. if this field represents a regist er, the lower four bits contain the modu le specifier and the upper four bits contain the register index in that module. bits 8 to 14 represent the destination for the transfer. this value always represents a destination register, with the lower four bits containing the module specifier and the upper three bits containing the regi ster subindex within that module. any time that it is necessary to directly select one of the upper 24 registers as a destination, the prefix register pfx is needed to supply the extra destination bits. this prefix register write is in serted automatically by the assembler and requires only one additio nal execution cycle. refer to the maxq family user's guide for complete instruction set information. memory organization the ds2792 incorporates several memory areas: ? 4k words of utility rom contain a debugger, program loader, and sha-1 routines ? 4k words of eeprom memory fo r application prog ram storage ? 256 words of sram for storage of temporary variables ? 64 words of eeprom memo ry for data storage ? 10 words of adc conversion data information ? 16-level stack memory for storage of progra m return addresses and general-purpose use the memory is implemented using the harvard architecture , with separate address spaces for program and data memory. a pseudo-von neumann memory map is also ut ilized placing rom, application code, and data memory into a single contiguous memory map. the pseudo-von neuman memory map allows data memory to be mapped into program space, permitting code execution from data memory. in addition, program memory can be mapped into data space, permitting code constants to be acce ssed as data memory. figure 3 shows the ds2792?s memory map when executing from program memory space. refer to the maxq family user's guide: ds2792 supplement for memory map information when executing from data or rom space.
ds2792 programmable fuel gauge with uart interface 9 of 40 the incorporation of eeprom memory allows field upgrade of the firmwa re. eeprom memory can be password protected with a 16-word key, denyi ng access to program memory by unauthor ized individuals. rom memory is also available for high-volume, low-cost applications. c ontact dallas semiconductor for more information on the availability of rom-based devices. figure 3. ds2792 memory map 16 16 stack ap system registers a pfx ip sp dpc dp 00h 0fh 8h 9h bh ch dh eh fh peripheral registers m0 m1 m2 00h 1fh 0h 1h 2h 4k 16 user program memory 0000h 0fffh 4k 16 utility rom 8000h 8fffh program memory space ffffh 256 16 sram data 0000h 00ffh 11 16 adc data 6000h 600ah data memory (word mode) ffffh 64 16 eeprom data 0100h 013fh 512 8 sram data 0000h 01ffh data memory (byte mode) ffffh 128 8 eeprom data 0200h 027fh 4k 16 utility rom 8000h 8fffh 8k 8 utility rom 8000h 9fffh stack memory a 16-bit, 16-level internal stack provi des storage for program return addresses and general-purpose use. the stack is used automatically when the call, ret, and reti instructions are execut ed and interrupts serviced. the stack can also be used explicitly to store and retrieve data by using the push, pop, and popi instructions. on reset, the stack pointer (sp) initializes to the top of the stack (0fh). the call, push, and interrupt-vectoring operations increment sp, then store a value at the location pointed to by sp. the ret, reti, pop, and popi operations retrieve the value pointed to by sp, and then decrement sp. utility rom the utility rom is a 4k word block of in ternal rom memory that defaults to a starting address of 8000h. the utility rom consists of subroutines that can be ca lled from application software. these include: ? in-system programming (bootstrap loader) over jtag or serial interfaces ? in-circuit debug routines ? internal self-test routines ? callable routines for in-a pplication eeprom programmi ng and sha-1 calculations following any reset, execution begins in the utility ro m. the rom software determi nes whether the program execution should immediately jump to location 0000h, the st art of application code, or to one of the special routines
ds2792 programmable fuel gauge with uart interface 10 of 40 mentioned. routines within the utility rom are firmware-accessible and can be called as subroutines by the application software. more information on t he utility rom contents is contained in the maxq family user's guide: ds2792 supplement . some applications require protection against unauthor ized viewing of program code memory. for these applications, access to in-system programming, in-applicat ion programming, or in-circuit debugging functions is prohibited until a password has been supplied. the passw ord is defined as the 16 words of physical program memory at addresses x0010h to x001fh. upon startup, code in the rom exam ines the password, if a password is defined (password is other than all zeros or all ones), and the pwl bit remains set, which prohibits access to commands to read memory contents over the jtag and serial interfaces. a single password lock (pwl) bit is implemented in the sc register. when the pwl is set to one (power-on reset default), the password is required to access the utility rom, including in-c ircuit debug and in-system programming routines that allow reading or writing of internal memo ry. when pwl is cleared to zero, these utilities are fully accessible without password. the password is automat ically set to all ones following a mass erase. programming the eeprom memory of the microcontroller can be pr ogrammed by two different methods: in-system programming and in-application programming. both methods afford great flexibility in system design as well as reduce the life-cycle cost of the embedded system. th ese features can be password protected to prevent unauthorized access to code memory. in-system programming an internal bootstrap loader allows the device to be prog rammed over the jtag or seri al interfaces. as a result, system software can be upgraded in-system, eliminating the need for a costly hardw are retrofit when software updates are required. remote software upl oads are possible that enable physically inaccessible applications to be frequently updated. the jtag interface hardware can be a jtag connection to another microcontroller, or a connection to a pc serial port using a serial to jtag converter such as the maxqjtag-001 (3.3v reference voltage required), available from maxim integrated products . the uart interface hardware can be a connection to another microcontroller, or a connection to a pc usb por t using a usb to uart converter such as the ds9123o, available from dallas semiconductor. a commercial gang programmer can also be used for programming. activating the jtag interface and loading the test ac cess port (tap) with the system programming instruction invokes the bootstrap loa der for use over the jtag interface. setti ng the spe bit to 1 during reset through the jtag interface executes the bootstrap-loader-mode program that resides in the utility rom. when programming is complete and the bootstrap loader exited, the spe bit will clear and the ic will reset, allowing execution of the application software. performing a program request over the serial interfac e also invokes the bootstrap loader. the user must successfully complete a password match (if pwl = 1). t he bootstrap loader functions are then fully supported over the serial interface. when programming is complete, the ex it loader function is used to reset the ds2792 and begin execution of the application software. the following bootstrap loader functions are supported: ? information commands ? load eeprom code and data ? dump eeprom code and data ? crc eeprom code and data ? verify eeprom code and data ? erase eeprom code and data
ds2792 programmable fuel gauge with uart interface 11 of 40 in-application programming the in-application programming feature allows the microcontroller to modify its own eeprom program memory. this allows on-the-fly software updates in mission-critical applicati ons that cannot afford downtime. alternatively, it allows the application to develop custom loader softwar e that can operate under the control of the application software. the utility rom contains fi rmware-accessible eeprom programming functions that erase and program eeprom memory. these functions are described in detail in the maxq family user's guide: ds2792 supplement . system timing the ds2792 generates its 1mhz instruction clock (osci) internally. this quick starting oscillator is used for instruction fetch and execution by the maxq20 core. the analog oscillator (osca) is a bandgap-based rc oscillator that is trimmed to better than 2% accuracy (f err:osca ). the analog clock runs independent of osci and serves as the clock source for the adc, watchdog timer, and interval timer. osca is enabled by the watchdog timer signals ewdi or ewt, by the timer/coun ter (tmod), or by the coulomb counter (ccen). osci is enabled through either a system interrupt or system por and disabled through a system stop. a voltage brownout-detection circuit disables osci if v dd falls below v bo . once v dd raises above v bo , a hysteresis circuit waits t su:osci before re-enabling osci. to improve overall sy stem timing and meet uart timing requirements, osci is slaved to osca when osca is active. figure 4. system clocks
ds2792 programmable fuel gauge with uart interface 12 of 40 system reset several reset sources are provided for microcontroller cont rol. although code execution is halted in the reset state, osci continues to run. power-on reset: an internal power-on reset circuit enhances system reliability. this circuit forces the device to perform a power-on reset whenever a rising voltage on v dd climbs above v por . at this point the following events occur: ? all registers and circuits enter their reset state. ? the por flag (wdcn.7) is set to indicate the source of the reset. ? code execution begins at location 8000h. watchdog timer reset: software can determine if a reset is caus ed by a watchdog timeout by checking the watchdog timer reset flag (wtrf) in the wdcn regist er. execution resumes at location 8000h following a watchdog timer reset. external system reset: asserting the external rst (port p0.2) pin low causes the device to enter the reset state. the external reset function is described in the maxq family user's guide . execution resumes at location 8000h after the rst pin is released. maxq20 core powe r management the ds2792 is designed for low-power battery-monitoring applications. the peripherals have been designed with the ability to wake the processor from sleep or analog mode any time so ftware intervention is needed. power management is optimized in the applications by performi ng any necessary processing as quickly as possible, and re-entering the low power sleep or analog mode. processing resu mes from sleep or analog mode via any of the following sources (when enabled): ? an external interrupt is triggered. ? an external reset signal is applied to the rst pin. ? a watchdog timer interrupt occurs. ? an internal interrupt event occurs. note: no division of the internal system clock is suppor ted, subsequently the pmme and cd[1:0] bits described in the maxq family user?s guide are not implemented in the ds2792. watchdog timer the watchdog timer provides a mechanism to reset the pr ocessor in the case of undesi rable code execution. the watchdog timer is a hardware timer designed to be periodica lly reset by the application software. if the software operates correctly, the timer is reset before it reaches its maximum count. however, if undesireable code execution prevents a reset of the watchdog timer, the timer re aches its maximum count and resets the processor. the watchdog timer in the ds2792 differs in two respects from the one described in the maxq family user's guide : 1) the clock used by the timer is the 70khz osca clock that runs independently of the 1mhz osci (or system) clock, and 2) the watchdog interrupt is an asynch ronous interrupt that can bri ng the processor out of stop mode. the watchdog timer is controlled through bits in the wdcn register. its timeout period can be set to one of the four programmable intervals ranging from 2 12 to 2 21 osca clock periods (59ms up to 30s). the watchdog interrupt occurs at the end of this timeout period, which is 512 osca clock periods, or 7.3ms, before the reset.
ds2792 programmable fuel gauge with uart interface 13 of 40 ds2792 power modes when power is first applied to the ds2792, a power-on-re set (por) circuit transitions the ic to brownout state where cell voltage is monitored. if v dd voltage is above the brownout threshold v bo , the ds2792 enters cpu mode and begins code execution. firmware det ermines if the ic switches to analog mode or low-power sleep mode when a stop halts cpu operation. the ds2792 enters sleep mode after a cp u stop if the adc and all internal timers are disabled and the suspend timer is off. in sleep mode, all ic operation becomes inactive except for external activity interrupts. brownout detection does not occur in sleep mode. any in terrupt generated by uart communication or external input on ports p0.0 or p0.1 will transition the ds2792 from sleep to brownout to verify cell voltage before returning to cpu mode. if the suspend timer is enabled, the ic will transition from sleep to analog mode if a suspend timeout occurs. the ds2792 enters analog mode after a cpu stop if any on e of the following is acti ve: the adc, the interval timer, or the watchdog timer. an external interrupt or an interrupt from any active internal circuit causes the ds2792 to transition back to cpu mode to service the condition. if the ds2792 is in analog or cpu mode, and v dd falls below v bo , a brownout condition occurs and the ds2792 enters the brownout state. in brownout state, the processo r is halted without changing the instruction pointer. if v dd voltage rises above v bo within a time of t su:osci , the ds2792 returns to cpu mode and generates a brown-out interrupt (if enabled). otherwise, if v dd remains below v bo for t su:osci , the ds2792 again enters sleep mode and waits to receive an interrupt. note that the supply rise time at initial power up of the ic must be faster than t su:osci to prevent the ds2792 from entering sleep mode prior to software enabling external inte rrupts. if this situation occurs, the ds2792 remains in sleep until power cycled. figure 5. ds2792 state diagram code execution cpu disabled. adc active external interrupts monitored b r o w n - o u t t i m e o u t t > t s u : o s c i brown-out vdd < v bo external interrupt cpu stop analog circuits inactive brown-out recovery vdd > v bo for t su:osci brown-out vdd < v bo interrupt power on reset cpu stop analog circuits active suspend timeout suspend timer enabled
ds2792 programmable fuel gauge with uart interface 14 of 40 suspend timer the suspend timer allows the ds2792 to periodically monitor the cell while spending the majority of its time in a low-power state. suspend operation is managed through the coulomb counter control register (cccon). a timout value between 0.5s and 2.0s can be selected through t he suspend timeout bits (ccs us). when the suspend timer is enabled and a timeout occurs, the ds2792 will transiti on from sleep mode to analog mode, and eventually to cpu mode. upon transition to analog mode, the coulomb counter enable bit (ccen) is automatically set and the adc block becomes active. the ds2792 may then perform a ll needed cell-monitoring operations before clearing the ccen bit and returned to sleep mode. t he process repeats after each timeout. figure 6. cccon register format field bit format allowable values reserved 7:3 read only undefined ccsus 2:1 r/w suspend timeout 0 0 = suspend timeout disabled 0 1 = 0.5s timeout 1 0 = 1.0s timeout 1 1 = 2.0s timeout ccen 0 r/w coulomb counter enable 0 = adc block disabled 1 = adc block enabled register set most functions of the device are controlled by sets of registers. these registers provide a working space for memory operations as well as configuring and addressing pe ripheral registers on the dev ice. registers are divided into two major types: system registers and peripheral registers. the common register set, also known as the system registers, includes the alu, accumulator registers, data pointers , interrupt vectors and control, and stack pointer. the peripheral registers define additional function ality that may be included by different products based on the maxq20 architecture. this functionality is broken up into discrete modules so that only the features required for a given product need to be included. tables 1 through 6 detail the ds2792 register set. table 1. system register map module name (base specifier) register index ap (8h) a (9h) pfx (bh) ip (ch) sp (dh) dpc (eh) dp (fh) 00h ap a[0] pfx ip ? ? ? 01h apc a[1] ? ? sp ? ? 02h ? a[2] ? ? iv ? ? 03h ? a[3] ? ? ? offs dp0 04h psf a[4] ? ? ? dpc ? 05h ic a[5] ? ? ? gr ? 06h imr a[6] ? ? lc0 grl ? 07h ? a[7] ? ? lc1 bp dp1 08h sc a[8] ? ? ? grs ? 09h ? a[9] ? ? ? grh ? 0ah ? a[10] ? ? ? grxl ? 0bh iir a[11] ? ? ? fp ? 0ch ? a[12] ? ? ? ? ? 0dh ? a[13] ? ? ? ? ? 0eh ckcn a[14] ? ? ? ? ? 0fh wdcn a[15] ? ? ? ? ? note: names that appear in italics indicate that all bits of a regist er are read-only. names that appear in bold indicate that a regi ster is 16 bits wide. registers in module ap are bit addressable.
ds2792 programmable fuel gauge with uart interface 15 of 40 table 2. system register bit functions register bit number register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ap ? ? ? ? ap (4 bits) apc clr ids ? ? ? mod2 mod1 mod0 psf z s ? gpf1 gpf0 ov c e ic ? ? cgds ? ? ? ins ige imr ims ? ? ? ? ? im1 im0 sc tap ? ? ? ? rod pwl ? iir iis ? ? ? ? ? ii1 ii0 ckcn ? ? ? ? ? ? ? ? wdcn por ewdi ? ? wdif wtrf ewt rwt a[n] (0..15) a[n] (16 bits) pfx pfx (16 bits) ip ip (16 bits) sp ? ? ? ? ? ? ? ? ? ? ? ? sp (4 bits) iv iv (16 bits) lc[0] lc[0] (16 bits) lc[1] lc[1] (16 bits) offs offs (8 bits) dpc ? ? ? ? ? ? ? ? ? ? ? wbs2 wbs1 wbs0 sdps1 sdps0 gr gr.15 gr.14 gr.13 gr.12 gr.11 gr.10 gr.9 gr.8 gr.7 gr.6 gr.5 gr.4 gr.3 gr.2 gr.1 gr.0 grl grl.7 grl.6 grl.5 grl.4 grl.3 grl.2 grl.1 grl.0 bp bp (16 bits) grs grs.15 grs.14 grs.13 grs.12 grs.11 grs.10 grs.9 grs.8 grs.7 grs.6 gr s.5 grs.4 grs.3 grs.2 grs.1 grs.0 grh grh.7 grh.6 grh.5 grh.4 grh.3 grh.2 grh.1 grh.0 grxl grxl.15 grxl.14 grxl.13 grxl .12 grxl.11 grxl.10 grxl.9 grxl.8 grxl.7 grxl.6 grxl.5 grxl.4 grxl.3 grxl.2 grxl.1 grxl.0 fp fp (16 bits) dp[0] dp[0] (16 bits) dp[1] dp[1] (16 bits)
ds2792 programmable fuel gauge with uart interface 16 of 40 table 3. system register bit reset values register bit register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ap 0 0 0 0 0 0 0 0 apc 0 0 0 0 0 0 0 0 psf 1 0 0 0 0 0 0 0 ic 0 0 0 0 0 0 0 0 imr 0 0 0 0 0 0 0 0 sc 0 0 0 0 0 0 s 0 iir 0 0 0 0 0 0 0 0 ckcn 0 s s 0 0 0 0 0 wdcn s s 0 0 0 0 0 0 a[n] (0..15) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pfx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ip 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sp 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 iv 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lc[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lc[1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 offs 0 0 0 0 0 0 0 0 dpc 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 gr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 grl 0 0 0 0 0 0 0 0 bp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 grs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 grh 0 0 0 0 0 0 0 0 grxl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dp0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dp1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: s indicates bit reflects pin state.
ds2792 programmable fuel gauge with uart interface 17 of 40 table 4. peripheral register map module module register index m0 (0h) m1 (1h) m2 (2h) register index m0 (0h) m1 (1h) m2 (2h) 00h po sint ? 10h ? ? ? 01h ppu smask ? 11h ? ? ? 02h paf ? ? 12h ? ? ? 03h eic smd ? 13h ? ? ? 04h eint sbuf ? 14h ? ? ? 05h cccon scon ? 15h ? ? ? 06h tc pr ? 16h ? ? ? 07h tcc ? ? 17h ? ? ? 08h pi ? ? 18h icdt0 ? ? 09h ? ? ? 19h icdt1 ? ? 0ah ? saden ? 1ah icdc ? ? 0bh ? saddr ? 1bh icdf ? ? 0ch ? bre ? 1ch icdb ? ? 0dh ? ? ecntl 1dh icda ? ? 0eh ? ? eaddr 1eh icdd ? ? 0fh ? ? edata 1fh ? ? ? note: names that appear in italics indicate that all bits of a register are read-only. name s that appear in bold indicate that a regi ster is 16 bits. all locations are bit addressable.
ds2792 programmable fuel gauge with uart interface 18 of 40 table 5. peripheral re gister bit functions register bit number register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 po ? ? po.5 po.4 po.3 po.2 po.1 po.0 ppu txd_pu rxd_pu ppu .5 ppu.4 ppu.3 ppu.2 ppu.1 ppu.0 paf ? rstd paf.5 paf.4 paf.3 paf.2 paf.1 paf.0 eic mboi msci msdi ? ? ? mvi mci mti mtci pip.1 pip.0 pit.1 pit.0 pie.1 pie.0 eint boi sci sdi ? ? ? vi ci ti tci ? ? ? rst int.1 int.0 cccon ? ? ? ? ? ccsus.1 ccsus.0 ccen tc thi.7 thi.6 thi.5 thi.4 thi.3 thi.2 thi.1 thi.0 tlow.7 tlow.6 tlow.5 tlow.4 tlow.3 tlow.2 tlow.1 tlow.0 ttc ? ? ? ? ? ttck.1 ttck.0 tmod pi ? rxdi pi.5 pi.4 pi.3 pi.2 pi.1 pi.0 icdt0 icdt0.15 icdt0.14 icdt0.13 icdt0.12 icdt0.11 icdt0.10 icdt0.9 icdt0.8 icdt0.7 icdt0.6 icdt0.5 icdt0.4 icdt0.3 icdt0.2 icdt0.1 ic dt0.0 icdt1 icdt1.15 icdt1.14 icdt1.13 icdt1.12 icdt1.11 icdt1.10 icdt1.9 icdt1.8 icdt1.7 icdt1.6 icdt1.5 icdt1.4 icdt1.3 icdt1.2 icdt1.1 ic dt1.0 icdc dme ? rege ? cmd.3 cmd.2 cmd.1 cmd.0 icdf ? ? ? ? pss.1 pss.0 spe txc icdb icdb.7 icdb.6 icdb.5 icdb.4 icdb.3 icdb.2 icdb.1 icdb.0 icda icda.15 icda.14 icda.13 icda.12 icda.11 icda .10 icda.9 icda.8 icda.7 icda.6 icda.5 icda.4 icda.3 icda.2 icda.1 icda.0 icdd icdd.15 icdd.14 icdd.13 icdd.12 icdd.11 icdd.10 icdd.9 icdd.8 icdd.7 icdd.6 icdd.5 icdd.4 icdd.3 icdd.2 icdd.1 icdd.0 sint ? ? ? ? ? ? tint rint smask ? ? ? ? ? ? mti mri smd ? ? txdi rxdi ? ? smod fede sbuf sbuf.7 sbuf.6 sbuf. 5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 scon fe/sm0 sm1 sm2 ren tb8 rb8 ti ri pr pr.15 pr.14 pr.13 pr.12 pr.11 pr.10 pr.9 pr.8 pr.7 pr.6 pr.5 pr.4 pr.3 pr.2 pr.1 pr.0 saden same.7 same.6 same.5 same.4 same.3 same.2 same.1 same.0 saddr sad.7 sad.6 sad.5 sad.4 sad.3 sad.2 sad.1 sad.0 bre bre.15 bre.14 bre.13 bre.12 bre.11 br e.10 bre.9 bre.8 bre.7 bre.6 bre. 5 bre.4 bre.3 bre.2 bre.1 bre.0 note: names that appear in italics indicate a read-only register bit.
ds2792 programmable fuel gauge with uart interface 19 of 40 table 6. peripheral register reset values register bit number register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 po 0 0 1 1 1 1 1 1 ppu 0 0 0 0 0 1 0 0 paf 0 0 0 0 0 1 0 0 eic 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 eint 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cccon 0 0 0 0 0 0 0 0 tc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ttc 0 0 0 0 0 0 0 0 pi s s s s s s s s icdt0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 icdt1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 icdc 0 0 0 0 0 0 0 0 icdf 0 0 0 0 0 0 0 0 icdb 0 0 0 0 0 0 0 0 icda 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 icdd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sint 0 0 0 0 0 0 0 0 smask 0 0 0 0 0 0 0 0 smd 0 0 0 0 0 0 0 0 sbuf 0 0 0 0 0 0 0 0 scon 0 0 0 0 0 0 0 0 pr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 saden 0 0 0 0 0 0 0 0 saddr 0 0 0 0 0 0 0 0 bre 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: s indicates bit reflects pin state. on-chip regulator the ds2792 provides a regulated 3.3v output on the v b pin capable of supplying up to 2ma of current to external circuitry. the regulated supply can be used to level shift t he i/o lines and/or provide a reference voltage for the vx pin to measure a pack id resistor or thermistor. the regul ator output is always active regardless of the ds2792?s mode of operation. system interrupts multiple interrupt sources are available for quick res ponse to internal and external events. the maxq20 architecture uses a single interrupt vect or (iv), single interrupt-service routi ne (isr) design. for maximum flexibility, interrupts can be enabled globally, individually, or by module. when an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the loca l, module, or global level. interrupt flags must be cleared within the firmware-interrupt routine to avoid repeated in terrupts from the same source. application software must ensure a delay between the write to the flag and the reti in struction to allow time fo r the interrupt hardware to remove the internal interrupt condition. asynchronou s interrupt flags require a one-instruction delay and synchronous interrupt flags requi re a two-instruction delay. when an enabled interrupt is detected, execution jumps to a user-programmable interrupt vector location. the iv register defaults to 0000h on reset or po wer-up, so if it is not changed to a different address, application firmware must determine whether a jump to 0000h came from a reset or interrupt source. once control has been transferred to the isr, the interrupt identific ation register (iir) can be used to determine if a system register or peripheral re gister was the source of the inte rrupt. the specified module can then be interrogated for the specific interrupt source and software can take appropriate action. interrupts are evaluated by application code allowing the definition of a unique interrupt priority scheme for each application. interrupt sources are available from the watchdog timer described in the maxq users guide , the sint register described in the uart interrupts section, and the eint register as shown in figure 7.
ds2792 programmable fuel gauge with uart interface 20 of 40 eint register the eint register contains interrupts generated by the adc, the timer counter, the general-purpose port pins, and the uart rxd pin. their masks and thei r configuration bits, along with the rst pin status and control, are present in the eic and paf registers of module 0. figure 7. eint register interrupt sources generator interrupt mask description frequency int0 paf.0/pie.0 the interrupt from pin p0.0 is configurable via the paf.0, pit.0, and pip.0 bits. dependent on external conditions. int1 paf.1/pie.1 the interrupt from pin p0.1 is configurable via the paf.1, pit.1, and pip.1 bits. dependent on external conditions. sci msci the serial connect interrupt is generated when rxd becomes high. rising edge on rxd. ports and pins sdi msdi the serial disconnect interrupt is generated when rxd is low for at least 220ms. once every 220ms if rxd is held low. the first interrupt may take up to 440ms from the time rxd goes low. interrupt will not trigger if the adc is off. brownout detector boi mboi the brownout interrupt indicates that v dd was below v bo in the past. it will not terminate the microcontroller's stop mode. it will interrupt the microcontroller, if mboi is 1, after a charger brings v dd above v bo and causes the microcontroller to run. every time after exiting brownout. vi mvi the voltage interrupt indicates the voltage registers in the data peripheral memory block have fresh voltage averages. once every 13.8ms. never if the adc is off. ci mci the current interrupt indicates that the current register (6004h) in the data peripheral memory block has a fresh reading and that the acr has also been updated. once every 88ms. never if the adc is off. a/d converter ti mti the temperature interrupt indicates that the temperature register in the data peripheral memory block has a fresh average. once every 220ms. never if the adc is off. timer/ counter tci mtci the timer/counter interrupt indicates that the timer/counter has been reloaded after reaching its end-count. dependent on tmod and ttck[1:0].
ds2792 programmable fuel gauge with uart interface 21 of 40 i/o ports the ds2792 includes a simple input/output (i/o) data port. from a software perspective, the port appears as a group of special-function registers within module m0. t he simple i/o port defined for this product is described below: ? cmos input buffers ? four open-drain output drivers with selectable tri-state or weak pullups ? two selectable open-drain or push-pull out put drivers with selectable tri-state ? support alternate functions and tap controller interface signals ? two pins have interrupt capability the port is accessed through five peripheral registers (po, pi, paf, ppu, and eic) addressed either by byte or by individual bit locations. the i/o port is designed to provi de programming flexibility for the application. all individual i/o pins are independently configured; and can be defin ed as an input, output, or alternate function. table 7 summarizes the functionality of the i/o pins. table 7. i/o port pins functions characteristics primary alternate tap * bidirectional weak passive pulldown weak active pullup strong active pullup p0.0 int0 tdi * configurable, [in] ? configurable, [off] ? p0.1 int1 tms * configurable, [in] ? configurable, [off] ? p0.2 rst* ? configurable, [in] ? configurable, [off] ? p0.3 ? tck * configurable, [in] ? configurable, [off] ? p0.4 ? tdo* configurable, [in] ? ? configurable, [off] p0.5 ? ? configurable, [in ] ? ? configurable, [off] txd ? ? output configurable , [on] configurable, [off] ? rxd ? ? input configurable, [on] configurable, [off] ? note: reset values are denoted with an * and by [ ]. pi register : the pi register is a read-only input of the i/o pins . when the register is read, the logic level of each pin is reported in the corresponding bit locations. reading a logic-low or high on a pin does not change the output drive on that pin. po register : the po register controls the out put state of the i/o pins. data wri tten to this register determines the pin output drive. when a bit is written to a ?0? (cleared) , the n-channel output drive transistor is enabled, and the pullup is disabled. when bit is written to a ?1? (set), t he n-channel output drive transistor is disabled, and the pullup enabled (if so configured). the po bits are set asynchronously during power-on reset to disable the n-channel output drive. po bits are not altered in sleep m ode, however drive to the n-channel is disabled. ppu register : the ppu register contains independent bits t hat define each pin as high impedance or pulled up when its n-channel output drive transistor is disabled. p0.0 through p0.3 have weak pullups, p0.4 and p0.5 have strong pullups. when the output is disabled and the ppu bi t is cleared, the pin is high impedance. when the output is disabled and the ppu bit is set, the pin?s weak or strong pullup is enabled. when the ppu bit is set and the device enters stop mode, the weak pullup remains enabled. paf register : the paf register enables or disables the alternat e functions of p0.0?p0.2. when a pin?s paf bit is cleared, the pin is controlled by the pi, po, ppu, and eic regi sters. when the paf bit is set, the pin operates in it?s alternate function mode. the rst function of p0.2 can be disabled by writing the rstd bit to 1. eic register : the lower six bits of the eic register are the port interrupt control bits. the port interrupt control bits are used to enable and configure detecti on of external interrupts. interrupt enable bits, pie.0 and pie.1, enable detection of an interrupt on pins p0.0 and p0.1, respecti vely. interrupt type bits, pit.0 and pit.1, define the type (level or edge) of interrupt on pins p0.0 and p0.1, respec tively. interrupt polarity bits, pip.0 and pip.1, determine the interrupt polarity on pins p0.0 and p0.1, respectively.
ds2792 programmable fuel gauge with uart interface 22 of 40 table 8. p0 interrupt configuration pie.x pit.x pip.x result 0 x x interrupt disabled 1 0 0 interrupt enabled, triggered on logic-low 1 0 1 interrupt enabled, triggered on logic-high 1 1 0 interrupt enabled, triggered on falling edge 1 1 1 interrupt enabled, triggered on rising edge figure 8. port pin schematics
ds2792 programmable fuel gauge with uart interface 23 of 40 programmable timer/counter the timer/counter block operates as a simple 8-bit interval timer or counter. the start value is programmable and is automatically reloaded when a rollover occurs. the tmod bit in the tcc register selects between the counter and timer modes. in the counter mode, external events on t he p0.3 pin are counted. in the timer mode, osca clock source cycles are counted. the osca clock and brownout detectors continue to run if the cpu is stopped. figure 9. timer/count er block diagram the timer low byte (tlow) is used to count input events, while the timer high byte (thi) is used to store the reload value. firmware must initialize tlow and thi with the same value for the first count to be the same as succeeding counts. tlow counts up until ffh is reached, it is then autom atically reloaded with the value in thi. thi remains unchanged unless modified by firmware. the clock source is selected with ttck[1:0] bits. table 9 describes the possible resolution and range of the timer. table 9. programmable timer configuration tmod ttck[1:0] clock period timer range (t x 2 8 ) 1 0 0 14.3s 3.66ms 1 0 1 343s 87.9ms 1 1 0 6.86ms 1.76s 1 1 1 220ms 56.3s 0 n/a counter mode
ds2792 programmable fuel gauge with uart interface 24 of 40 serial interface module the ds2792 supports a universal asynchronous receiver/transmitter (uart) module for serial communication with framing error detection and automatic ad dress recognition. the uart is initia lized through a config uration register (smd). communication is managed through a control register (scon) and a transmit/receive register (sbuf). the sbuf register location provides access to both transmit a nd receive registers, where a read is directed to the receive buffer and a write is directed to the transmit buffer. sbuf allows the serial interface to receive an incoming word before software has read the previous one provided sbuf is read before the stop bit of the next word is recieved. if the ds2792 detects a start bit of an incoming transmission while in sleep mode, the instruct ion clock will be enabled to allow reception of data. note that the instruction clo ck will not achieve accuracy tolerance required for uart communication unless the analog oscillator is also active. all out going transmission must be completed, and the rxd pin must be in the inactive logic state (see rx di bit), before the ds2792 will transition back to sleep mode. figure 10. serial interface control register (scon) field bit format allowable values fe/sm0 7 r/w serial interface mode bit 0/framing error flag the operation of this bit depends on the state of the fede bit of the smd register. when fede is cleared to 0, this bit functions as sm0 and controls the operating mode. see serial interface modes , table 10. when fede is set to 1, this bit functions as a framing error flag and will automatically be set to 1 when the incoming stop bit has been received as a logic 0. when used as fe, this flag must be cleared to 0 by software. sm1 6 r/w serial interface mode bit 1 see serial interface modes , table 10 sm2 5 r/w serial interface mode bit 2 mode 1 operation: 0 = normal operation 1 = rxi flag not set if incoming stop is logic 0 modes 2 and 3 operation: 0 = multiprocessor mode disabled 1 = multiprocessor mode enabled ren 4 r/w reciever enable 0 = reciever enabled 1 = reciever disabled tb8 3 r/w transmit data bit 8 when in mode 2 or 3, this bit determines the state of the ninth transmitted data bit. this bit is not used in mode 1. rb8 2 r/w received data bit 8 when in mode 2 or 3, this bit indicates the state of the incoming ninth data bit. in mode 1, this bi t indicates the state of the stop bit. ti 1 r/w transmit interrupt flag set to 1 at the end of the last data bit transmitted. ti must be cleared by software. ri 0 r/w recieve interrupt flag set to 1 at the end of the stop bit sampling window when in mode 1. set to 1 at the end of the sampling window of the ninth data bit when in mode 2 or 3. ri must be cleared by software.
ds2792 programmable fuel gauge with uart interface 25 of 40 figure 11. serial interface c onfiguration register (smd) field bit format allowable values reserved 7:6 read only undefined txdi 6 r/w txd invert bit 0 = normal operation 1 = txd output signal inverted rxdi 5 r/w rxd invert bit 0 = normal operation 1 = rxd input data inverted reserved 3:2 read only undefined smod 1 r/w baud rate doubler 0 = baud rate divided by 2 (mode 2) 0 = baud rate divided by 4 (modes 1 and 3) 1 = baud rate unchanged fede 0 r/w framing error enable flag 0 = sicon bit 7 controls communication mode (sm0) 1 = sicon bit 7 flags framing errors (fe) figure 12. serial in terface block diagram d0 start d7 stop d8 modes 2&3 only stop bit (mode 1) d8 (modes 2&3) input shift register bit detect d0 d7 sbuf input register d0 start d7 stop d8 modes 2&3 only sbuf output shift register 16 rb8 rxd bit latch txd ren tb8 baud clock ti ri start detect
ds2792 programmable fuel gauge with uart interface 26 of 40 serial interface modes of operation the uart operates in one of three asynchronous full- duplex communication modes with different protocols and baud rates. two mode bits (sm1, sm0 in the scon register) are used to select the modes of operation. the operating modes are summarized in table 10. table 10. serial interface modes sm1 sm0 mode function clock length start/stop 9th bit function 0 1 1 asynchronous full duplex phase delta register 8 1 start, 1 stop n/a 1 0 2 asynchronous full duplex instruction clock 9 1 st art, 1 stop tb8, rb8 1 1 3 asynchronous full duplex phase delta register 9 1 start, 1 stop tb8, rb8 mode 1 mode 1 is asynchronous, full duplex with a 10-bit data str eam consisting of a logic 0 start bit, eight data bits, and logic 1 stop bit. the data is transferred least significant bi t first. the uart begins transmission several cycles after the first baud clock of the baud rate generator following a write to sbuf. transmission on the txd pin begins with the start bit, data then is shifted out on t he pin, least significant bit first, followe d by the stop bit. the ti bit is set tw o clock cycles after the stop bit is transmitted. all bits are shifted out at the rate determined by the baud rate generator. baud rate generation is discussed in the baud rate generation section. once the baud rate generator is active, reception can begin at any time. the ren bit in scon must be set to logic 1 to enable the reception. the falling edge of a start bit on the rxd pin will begin the reception process. data will be shifted in at the selected baud rate. at the middle of the st op bit time slot, certain conditions must be met to load sbuf with the received data from the receive shift register: ? ri must be 0, and ? if sm2 is 0, the state of t he stop bit does not matter, or ? if sm2 is 1, the state of the stop bit must be 1 if these conditions are true, the sbuf register will be loaded with the received byte, the rb8 bit will be loaded with the stop bits and the ri bit will be set. if these conditi ons are false, then sbuf and rb8 will not be loaded, the received data will be lost and the ri bit will not be set. regardl ess of the receive word status, the receive logic will go back to looking for a 1 to 0 transition on the rxd pin after the middle of the stop bit time. each data bit received is sampled on the 7th, 8th, and 9th clock from the baud rate generator (running 16 times faster than communication speed). using majority voting, two equal samples out of the three determine the logic value for each received bit. if the start bit was determined to be invalid, then the receive logic returns to looking for a 1 to 0 transition on the rxd pin in order to start the reception again.
ds2792 programmable fuel gauge with uart interface 27 of 40 figure 13. timing diagram fo r serial interface mode 1 mode 2 mode 2 is asynchronous, full-duplex communication with an 11 -bit data stream consisting of a logic 0 start bit, eight data bits, a programmable 9th bit, and a logic 1 stop bit. the data is transferred least significant bit first. similar to mode 1, transmissions occur on the txd pin and reception on the rxd pin. for transmission purposes, the 9th bit can be configured as logic 0 or 1. a common use is to load this location with a parity bit. the 9th bit is transferred from the tb8 bit position in the scon register during the write to sbuf. the uart will begin transmission a few cycles after the first rollover of the clock source divided by 16 following a write to sbuf. transmission begins with the start bit being placed on the txd pin, data is then shi fted onto the pin, least significant bit first, followed by the 9th bit, and finally the stop bit. the ti bit is set at the sa me time the stop bit is transmi tted on the txd pin. all bits are shifted out at the rate determined by the baud rate generator. baud rate generation is discussed in the baud rate generation section. once the baud rate generator is active, reception can begin at any time. the ren bit must be set to a logic 1 to enable the reception. the falling edge of a start bit on t he rxd pin will begin the reception process. data will be shifted in at the selected baud rate. at the middle point of the 9th bit time slot, certain condition must be met to load sbuf with the received data from the receive shift register: ? ri must be 0, and ? if sm2 is 0, the state of t he stop bit does not matter, or ? if sm2 is 1, the state of the 9th bit must be 1
ds2792 programmable fuel gauge with uart interface 28 of 40 if these conditions are true, then sbuf will be loaded with t he received byte, the rb8 bit will be loaded with the 9th bit, and the ri bit will be set. if these conditions are fals e, then sbuf and rb8 will not be loaded, the received data will be lost, and ri bit will not be set. rega rdless of the receive word status, the receive logi c will go back to looking for a 1 to 0 transition on the rxd pin after the middle point of the stop bit time slot. each data bit received is sampled on the 7th, 8th, and 9th clock from the baud rate generator (running 16 times faster than communication speed). using majority voting, two equal samples out of the three determine the logic value for each received bit. if the start bit was determined to be invalid, then the receive logic goes back to looking for a 1 to 0 transition on the rxd pin in order to start the reception again. mode 3 operation of mode 3 is identical to mode 2 except for the baud rate source. baud rate generation is discussed in the baud rate generation section. figure 14. timing diagram for se rial interface modes 2 and 3 start d1 d0 d8 stop transmit frequency serial interface clock source divided by 16 d2 d3 d4 d5 d6 d7 7 th , 8 th , and 9 th samples of each bit start d1 d0 d8 stop transmit frequency serial interface clock source divided by 16 d2 d3 d4 d5 d6 d7 detection of framing errors a framing error occurs during communication when a valid stop bit is not detected. the result is a possible improper reception of t he serial word. the serial inteface will notify t he system by setting the framing error (fe) bit in the scon register to 1. when set, the fe bit must be cleared by software or a system reset. receiving a properly framed serial word will not clear the fe bit.
ds2792 programmable fuel gauge with uart interface 29 of 40 note that both the fe and the serial mode bit 0 (sm0) share the same bit location in the scon register, but this information is actually stored in different registers. the setting of fede in the smd register determines which register is accessed: logic 0 allows access to the sm0 bit and a logic 1 a llows access to the fe bit. the fede must be set to 1 while reading or writing the fe bit. multiprocessor communication mode multiprocessor communication mode makes special use of the 9th data bit in modes 2 and 3 if the sm2 bit of the scon register is set. if enabled, the 9th data bit is used to signify that the incoming byte is an address. this allows the processor to be interrupted only if the correct addres s is received as defined by the serial address (saddr) and serial address enable (saden) registers. the receiv e interrupt, if enabled, will only occur when a recognized address is received. when multiprocessor mode is enabled and a serial word is received with the 9th bit set, the byte will be assumed to be an address. the addre ss will be compared to an interna lly stored address. if it matc hes, a receive interrupt will occur. the internal address is derived from the saddr and saden registers. the saddr register specifies an absolute address. this is the user s pecified address of the device. the sad en register indicates which address bit(s) will be used in the comparison. th is allows broadcast transmissions that reach mult iple microcontrollers or all microcontrollers on the serial interfac e. the user defines this protocol. software will write an 8-bit address to th e saddr register. this is the microcontroller?s individual address. any bit in saden that contains logic 0 will cause the corresponding bit in saddr to be ignored in comparison. thus, logic 0 bits in saden create don?t care bit states for addr ess comparisons. when an addres s is received, each address bit that is not masked by a don?t care will be compared to the saddr. the microcont roller will interrupt on any address that matches this comparison. any address that meets this comparison is called a given address. the following example shows how one address can be direct ed to an individual processor or two out of three. micro 1 micro 2 micro 3 saddr 11110000 saddr 11110001 saddr 11110010 saden 11111010 saden 11111001 saden 11111010 ??????????????? ??????????????? ??????????????? given 11110x0x given 11110xx1 given 11110x1x note that an address of 11110000 reaches only microcont roller 1. an address of 11110001 reaches microcontroller 1 and microcontroller 2. an address of 11110010 reaches only microcontroller 3. the microcontroller also matches on any address that corresponds to t he broadcast address. this is the logical or of the saddr and saden registers, with any 0s defined as don?t cares. uart interrupts interrupts generated by the serial interface are controlled th rough the serial interface interrupt register (sint) and the serial interface inte rrupt mask register (smask). writi ng either the receive interrupt mask (mri) bit or transmit interrupt mask (mti) bit to 1 will enable interrupts to o ccur whenever the correspondi ng transaction successfully completes. writing either of these bi ts to 0 disables the corresponding inte rrupt. the rint, tint bits of the smask are a logical and of the ri flag, ti flag bits of the control register, and the corresponding interrupt mask bits. upon successful reception of a data wo rd on rxd, the ri flag of the scon re gister will be set. if mri is set to 1, the rint flag will be set and an interrupt will be generated. system software can then read the sint register to determine the source of the interrupt. the rint flag and the in terrupt are cleared by writing the ri flag to 0. after transmission of a data word on tx d, the ti flag of the scon register will be set. if mti is set to 1, the tint flag will be set and an interrupt will be generated. system software can then read the si nt register to det ermine the source of the interrupt. the tint flag and the interrupt are cleared by writing the ti flag to 0.
ds2792 programmable fuel gauge with uart interface 30 of 40 command codes the ds2792 has two reserved command codes: a software power-on reset (por) of the ic and an instruction to begin program loading over the serial interface. each co mmand code is enabled by transmitting a , 0xfe, , followed directly by the command instruction. there are no associated data bytes with either command. any other serial communication between the in structions negates the operation. see the maxq family user's guide: ds2792 supplement for the serial interface programming procedure. these command codes are fixed inside the ds2792 and cannot be altered. system firmwa re should avoid using feh as a command code during device operation. a in struction is defined as holding the rxd li ne low until a framing error is generated. table 11. serial interface command codes command hex code purpose command enable , feh, enable soft por or program command. soft por feh causes a reset of the ic. request programming fdh initiates prog ramming over the serial interface. available 00h?fch, ffh defined by application firmware. baud rate generation the baud rate for serial communication is derived directly from the instruction oscillator osci. the method for baud rate generation depends on the serial interface?s operati ng mode. in operating modes 1 and 3, the baud rate is determined by the value stored in the phase delta (pr) regi ster. in operating mode 2, the osci oscillator sets the baud rate directly. the baud rate doubler (smod) bit in t he smd register can be used to double the baud rate in mode 2 or quadruple the baud rate in modes 1 and 3. note that the baud clock frequency generated by this circuit will be the sampling frequency us ed by the serial interface and is therefore 16 times the actual communication rate. figure 15. baud rate generation circuit in mode 2, baud rates are generated dire ctly from the system clock. the b aud rate for mode 2 is given by the formula: baud rate = (2 smod 32) f osci . the result of this formula generates a baud rate of either 1/16 or 1/32 of the system clock frequency. in the ab ove formula, the numerator is expres sed as two to the power of smod, where smod is either a 0 or 1. the smod bit effectively doubles the baud rate when set to logic 1. the smod bit is set to logic 0 on reset, which gives the lower speed baud rate.
ds2792 programmable fuel gauge with uart interface 31 of 40 in modes 1 and 3, the baud rate generator creates a phase accumulator that generates a baud clock as the result of phase overflow into the most significant bit of the phase shift circuitry. as shown in figure 15, a 16-bit phase delta register (pr) is used to select a suitable phase del ta for its baud clock. the phase delta is used to provide a predetermined phase increment to the phase accumulator. the phase accumulator is formed by a 17-bit register and a 16-bit adder. when the baud rate generator is enabled, the content of the phase delta register adds to the value of the 17-bit register triggered by the system cl ock, essentially performing a phase accumulation. the baud clock is the result of the adder carry output to the most si gnificant bit of the 17-bit register. the baud rate for modes 1 and 3 are given by the formula: baud rate = (pr f osci ) 2 23 2 (smod2) . the smod bit effectively quadruples the baud rate when set to logic 1. the smod bit is set to logic 0 on reset, which gives the lower speed baud rate. table 12. sample baud rate settings mode smod pr register baud rate 2 0 n/a 30583 baud 2 1 n/a 61166 baud 1 or 3 1 1416h 2400 baud 1 or 3 1 282dh 4800 baud 1 or 3 1 505bh 9600 baud 1 or 3 1 a0b7h 19200 baud 1 or 3 0 282dh 1200 baud baud rate calculations are based on a system clock frequency of 978.656khz. note that the analog oscillator must be active for reliable serial communication. if osca is inactive, the osci timebase error f err:osci may be greater than the uart communication standard of 3%. baud rate error adjustment the baud rate error (bre) register provides error informati on that can be used by software to correct small errors in the ds2792?s baud rate compared to the transmitting ic?s baud rate by adjusting the value loaded in the phase delta register. at the end of each data word successfully received, the bre register is updated with a 0.125% resolution two?s complement value representing the perce nt difference between the expected final logic transition on txd compared to the final logic transition as measured by the bit sampler. a positive error means the uart is running too slow and a negative error means the uart is running too fast. figure 16. baud rate e rror register format s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb ?s?: sign bit(s) units: 2 0 = 0.125% for example: communication is occurring at 9600 baud (p r register contains 505bh) in mode 1, and a value of c5h is received by the uart. the final rxd transition betwe en bit d7 (logic 0) and the stop bit (logic 1) is expected to occur between sample 16 of the 7th bit and sa mple 1 of the 8th bit. after transmission is complete, the bre register is found to contain a value of 08h indicating the final logic transition occurred 1.0% early. the master is transmitting data at a rate of roughly 1.0% faster than the ds2792?s present baud rate. the pr register is updated to a value of 5129h (101% of 505bh) to correct t he transmission rate difference. it is recommended that the pr register is adjusted by only a fraction of the calculat ed error amount after each byte to prevent oscillation of the frequency setting. note that for dynamic baud rate error adjustment to be su ccessful, the starting frequency difference must be within ? bit period at the final logic transition point (50% if the final transition is between start and d0, 25% if the final transition is between d0 and d1, etc). the bre register is read only and is cleared on reset.
ds2792 programmable fuel gauge with uart interface 32 of 40 analog-to-digital conversion the ds2792 performs real-time measurements of system temp erature, voltage, current, and accumulated current. the ds2792?s adc is controlled by an internal state mach ine that sequences the measurements, and stores the results in memory. the conversion re sults of the adc are mapped into data memory starting at word address 6000h, as shown in table 13. the ds2792 current measurement system is designed to prov ide timely data on charge and discharge current at a moderate resolution level while simultaneously accumula ting high resolution average data to support accurate coulomb counting. current is measured by sampling the voltage drop across a series sense resistor, r sns , connected between sns1 and sns2. individual current samples are taken every 1/f sample (687s). all samples are averaged to report current, average curr ent, and accumulated current values. the ds2792 measures voltage on three separate inputs. the voltage of the lower cell, vin1, is reported as the measured difference between the vin1 pin and analog ground pin av ss . the voltage of the upper cell, vin2, is reported as the difference between the vin2 and vin1 pi ns. the auxiliary voltage, vx, is reported both as an absolute value of the difference between the vx pin and avss, and as a ratio metric pe rcentage of the voltage of the v b pin. individual voltage samples are taken approximately every 5/f sample (3.43ms). multiple samples are averaged to update the volt age measurement registers. the ds2792 measures temperature directly on chip. individual temperature samples are taken every 10/f sample (6.87ms). multiple samples are averaged to update the average temperature register. table 13. adc related registers word address access description 6000h read only vx voltage ratiometric 6001h read only vx voltage absolute 6002h read only vin2 voltage 6003h read only vin1 voltage 6004h read only current 6005h read only temperature 6006h r/w accumulated current 6007h read only accumulated current (middle word) 6008h read only accumulated current (lower word) 6009h read only average current 600ah r/w adc configuration current measurement the voltage signal developed across the sense resistor ( between sns1 and sns2) is differentially sampled by the adc inputs via internal 10k ? resistors connected between sns1 and is1, and sns2 and is2. isolating the adc inputs (is1 and is2 pins) from the sense resistor with 10k ? facilitates the use of an rc filter by adding a single external capacitor. the rc filter extends the effectiv e input range beyond 64mv in pulse load or pulse charge applications. the adc accurately measures large peak sign als as long as the differential signal level at is1 and is2 does not exceed 64mv. the current register reports the av erage of 128 individual current samp les every 88ms. the reported value represents the average current during the 88ms measurement period. figure 17 specifies the update interval and resolution of the current register. valu es are posted in two?s complement form at. positive values represent charge currents (v is1 > v is2 ) and negative values repres ent discharge currents (v is2 > v is1 ). positive currents above the maximum register value are reported at the maximum val ue, 7fffh. negative currents below the minimum register value are reported at the minimum value, 8000h.
ds2792 programmable fuel gauge with uart interface 33 of 40 figure 17. current register format 12-bit + sign resolution (13-bit), 88ms update interval word address 6004h s 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x msb lsb ?s?: sign bit(s) units: 2 0 = 15.625 v/r sns current resolution (1 lsb) r sns |v ss - v sns | 25m ? 20m ? 15m ? 10m ? 15.625v 625a 781a 1.042ma 1.56ma current input range r sns v ss - v sns 25m ? 20m ? 15m ? 10m ? 64mv 2.56a 3.2a 4.27a 6.40a the average current register reports the average of 4096 current samples over a 2.8s measurement period. figure 18 specifies the update interval and resolution of the av erage current register. values are posted in the same format as the current register, but with an additional 3 bits of resolution. positive currents above the maximum register value are reported at the maximum value, 7fffh. negative currents below the minimum register value are reported at the minimum value, 8000h. figure 18. average current register format 15-bit + sign resolution (16-bit), 2.8s update interval word address 6009h s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb ?s?: sign bit(s) units: 2 0 = 1.953 v/r sns average current reso lution (1 lsb) r sns |v ss - v sns | 25m ? 20m ? 15m ? 10m ? 1.953v 78.13a 97.66a 130.2a 195.3a automatic current offset correction continuous offset cancellation is performed automatically to correct for offsets in the current measurement system. individual values reported by the current register have a maxi mum offset of 0.5 bits (7.8125v). individual values reported in the average current register have a maximum offset of 4 bits (7.8125v).
ds2792 programmable fuel gauge with uart interface 34 of 40 current measurement bias systematic errors or an application preference can require the application of an arbitrary bias to the current measurement process. the current meas urement bias value sets a user-programmed positive or negative bias to the current measurement. the current measurement bias value can be used to estimate battery currents that do not flow through the sense resistor, estimate battery self -discharge, or correct for o ffset error in the current registers. the user-programm ed two?s complement value is added to the current register once per current sample. the bias control is applied in 0.98 v increments over a 125 v range. when using a 15m sense resistor, the bias control can be adjusted in 65.3 a increments over a 8.33ma range. the current measurement bias bit field is located in the upper byte of the adc configuration register. figure 19. current measu rement bias field upper byte of word address 600ah s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb ?s?: sign bit units: 2 0 = 0.98 v/r sns current accumulation current measurements are internally accumulated and disp layed in the accumulated cu rrent register (acr). the accuracy of the acr is dependent on both the current measurement and the accumulation time base. the 16-bit acr has a range of 204.8mvh with a resolution of 6. 25vh. accumulation of charge current above the maximum register value is reported at the maximum value; conver sely, accumulation of discharge current below the minimum register value is reported at the minimum value. read and write access is allowed to the acr. figure 20. accumulated current register format word address 6006h s 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb ?s?: sign bit(s) units: 2 0 = 6.25 vh/r sns acr resolution (1 lsb) r sns |v ss - v sns | / r sns 25m ? 20m ? 15m ? 10m ? 6.25vh 0.25mah 0.312mah 0.416mah 0.625mah acr accumulation range r sns |v ss - v sns | / r sns 25m ? 20m ? 15m ? 10m ? 204.8mvh 8.192ah 10.24ah 13.65ah 20.48ah
ds2792 programmable fuel gauge with uart interface 35 of 40 the lower 32 bits of acr resolution (bits 2 -1 to 2 -32 ) can be read by firmware from address locations 6007h and 6008h respectively. note that since the lower bits are from separate address words it cannot be guaranteed that they will contain data from the same m easurement as the main acr register at the time of reading. however, two consecutive reads from addresses 6006h?6008h that contain the same data ensures that all data is from the same measurement. when the acr register is written, the lower acr bits are automatically cleared. accumulation blanking in order to avoid the accumulation of small positive offs et errors over long periods, an offset blanking filter is provided. the blanking filter is enabled by setting the oben bit in the adc configurati on register. when oben is set, charge currents (positive values fr om the current register) less than 62.5 v are not accumulated in the acr. the minimum charge current accumulated in the acr is 4.167ma for r sns = 0.015 . voltage measurements the ds2792 continually measures the voltage between pins vin1 and av ss and between pins vin2 and vin1 over a 0.0v to v fs range. the vin1 and vin2 voltage registers are updated in two?s complement format every 13.8ms with a resolution of 4.88mv. voltages above the maximu m register value are reported as the maximum value. figure 21. vin1 voltage register format word address 6003h s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb ?s?: sign bit units: 2 0 = 4.88 mv figure 22. vin2 voltage register format word address 6002h s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb ?s?: sign bit units: 2 0 = 4.88 mv the ds2792 continually measures the voltage between pins vx and v ss . the result is reported in two?s complement absolute and ratiometric formats every 20ms. t he vx ratiometric voltage result is a ratio of voltage on the vx pin relative to the voltage on the v b pin. the lsb weighting is v b /1024. the vx absolute voltage result uses the internal reference and has a resolution of 4.88mv. vo ltages above the maximum register value are reported as the maximum register value. figure 23. vx ratiomet ric register format word address 6000h s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb ?s?: sign bit units: 2 0 = v b /1024
ds2792 programmable fuel gauge with uart interface 36 of 40 figure 24. vx absolute voltage register format word address 6001h s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb ?s?: sign bit units: 2 0 = 4.88 mv temperature measurement the ds2792 uses an integrated temper ature sensor to continually measur e battery temperature. temperature measurements are updated in the temperat ure register every 220ms in two?s complement format with a resolution of 0.125c over a 127c range. the temperature register format is shown in figure 25. figure 25. temperature register format word address 6005h s 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x x msb lsb ?s?: sign bit units: 2 0 = 0.125 c adc configuration register the adc configuration register located at word addre ss 600ah controls current measurement bias and offset blanking. adc configuration register bits are read and write accessable by application code. ibias bits are described in the current measurement bias section above. offset blanking is c ontrolled by the oben bit. if offset blanking is enabled, the ds2792 assumes small positive cu rrents do not occur in the application. small positive readings are considered a/d measurement error and are not accumulated. figure 26. adc configurat ion register format address 600ah bit definition field bit format allowable values ibias 15:8 r/w current measurement bias 8-bit two?s complement value that is added to the current measurement on every update. reserved 7:1 read only undefined oben 0 r/w offset blanking enable 0 = all current measurements are accumulated into the acr. 1 = positive current measurements less than 62.5v/r sns are not accumulated into the acr. password-protected user trim system software can change current m easurement gain, power-up state of the uart, and undervoltage threshold of the ic through the user trim in program eeprom (w ord addresses 001eh?001fh). t he user trim values are enabled through the trim key in the lower byte of address 001f h. if the trim key is set to 76h, the user-trim values replace the default trim values, if the trim key is set to any other value, default trim is selected. note that either all user-trim values are enabled or none are enabled. figure 27 shows the format of all values that can be adjusted and their default trim values.
ds2792 programmable fuel gauge with uart interface 37 of 40 figure 27. user trim registers address 001eh bit definition field bit format allowable values ig 15:8 r/w current gain trim these bits adjust the current gai n by 25%. the most significant bit is the two?s complement sign bit, 1 lsb = 0.195%. example: a4h (-92d) adjusts the trim by -17.94%. valid only if trim key = 76h default = factory trim value srtc 7:0 r/w sense resistor temperature coefficient these bits adjust the current gain based on temperature of the sense resistor. 1 lsb = 30.5ppm/oc. example: 1ah (26d) adjusts current measurements for a sense resistor with a 793ppm/oc temperature coefficient. valid only if trim key = 76h default = 00h address 001fh bit definition field bit format allowable values bd9600 15 r/w force uart baud rate at power-on reset 0 = 19200 baud 1 = 9600 baud valid only if trim key = 76h default = 0 txdi 14 r/w txdi bit power-on reset value 0 = normal operation 1 = txd output signal inverted valid only if trim key = 76h default = 0 rxdi 13 r/w rxdi bit power-on reset value 0 = normal operation 1 = rxd input data inverted valid only if trim key = 76h default = 0 uvt 12:8 r/w undervoltage threshold the undervoltage threshold ranges from 4.60v to 5.80v and is calculated by the equation: v uv = 5.80v - 0.039v uvt[4:0] valid only if trim key = 76h default = 17h (2.45v) trim key 7:0 r/w trim key enables or disables all other user-trim values. 76h = all user trim values valid other = all user trim values invalid (default trim used)
ds2792 programmable fuel gauge with uart interface 38 of 40 in-circuit debug embedded debugging capability is available through the jtag-compatible test access port. embedded debug hardware and embedded rom firmware provide in-circuit de bugging capability to the user application, eliminating the need for an expensive in-circuit emulator. figure 28 sh ows a block diagram of the in-circuit debugger. the in- circuit debug features include: ? a hardware debug engine. ? a set of registers able to set breakpoints on register , code, or data accesses (icda, icdb, icdc, icdd, icdf, icdt0, and icdt1). ? a set of debug service routines stored in the utility rom. figure 28. in-circuit debugger the embedded hardware debug engine is an independent hardware block in the microcontroller. the debug engine can monitor internal activities and interact with selected internal registers while the cpu is executing user code. collectively, the hardware and softw are features allow two basic m odes of in-circuit debugging: ? background mode allows the host to c onfigure and set up the in-circuit debugger while the cpu continues to execute the application software at full speed. debug mode can be invoked from background mode. ? debug mode allows the debug engine to take control of the cpu, providing read/write access to internal registers and memory, and si ngle-step trace operation.
ds2792 programmable fuel gauge with uart interface 39 of 40 applications the low-power, high-performance risc architecture of t he ds2792 makes it an excellent fit for many portable or battery-powered applications that r equire cost-effective computing and an alog measurement capability. the high- throughput core is programmable in circuit over the uart and jtag interfaces, allowing for firmware upgrades and ease of code development. applications benefit fr om uart and gpio peripheral interfaces allowing the microcontroller to communicate with many external devices. the ds2792?s high level of integration reduces component count and board space, critical fa ctors in the design of portable systems. the ds2792 is ideally suited for applications such as fuel gauging, sensor conditioning, and data collection. additional documentation designers must have four documents to fully use all the features of this device. this data sheet contains pin descriptions, feature overviews, and electrical specifications. errata sh eets contain deviations from published specifications. the user?s guides offer detailed inform ation about device features and operation. the following documents can be downloaded from www.maxim-ic.com/ds2792 . ? the ds2792 data sheet, which contains electrical/timing specifications and pin descriptions, available at www.maxim-ic.com/ds2792 . ? the ds2792 errata sheet, available at www.maxim-ic.com/errata . ? the maxq family user's guide , which contains detailed information on core features and operation, including programming at www.maxim-ic.com/products/maxqug . ? the maxq family user's guide: ds2792 supplement , which contains detailed information on features specific to the ds2792 at www.maxim-ic.com/ds2792ug . development and technica l support a variety of highly versatile, affordably priced developm ent tools for this microcontroller are available from maxim/dallas semiconductor and third-party suppliers, including: ? compilers ? in-circuit emulators ? integrated development environments (ides) ? serial-to-jtag converters for programming and debugging ? usb-to-jtag converters for programming and debugging technical support is available through email at batterymanagement.support@dalsemi.com .
ds2792 programmable fuel gauge with uart interface 40 of 40 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2007 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated produ cts, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. pin configuration 1 3 2 4 8mm 4mm tdfn-28 5 7 6 8 9 11 10 12 13 14 ds2792g+ 28 26 27 25 24 22 23 21 20 18 19 17 16 15 pad nc vin2 vin1 vx txd rxd nc nc nc nc tdi/int0/p0.0 tms/int1/p0.1 sns2 is2 nc vdd nc nc vb p0.5 p0.4/tdo nc p0.3/tclk p0.2/rst vss avss sns1 is1 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo .)
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs ds2792 part number table notes: see the ds2792 quickview data sheet for further information on this product family or download the ds2792 full data sheet (pdf, 540kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds2792g+ tdfn;28 pin;157 dwg: 56-g0011-001a (pdf) use pkgcode/variation: t2848+1 * -40c to +85c rohs/lead-free: yes ds2792g+t&r tdfn;28 pin;157 dwg: 56-g0011-001a (pdf) use pkgcode/variation: t2848+1 * -40c to +85c rohs/lead-free: yes didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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